This invention relates generally to integrated circuits, and in particular to systems and methods for preventing late-arriving control signals from initiating an intermediate, potentially destructive state between an initial state and an intended final state.
A logic control circuit switches between or among circuit states when input control signals make transitions between signal states. These circuit states may be classified either as non-destructive or as potentially destructive. For example, a circuit state in which a write enable signal is transmitted from the control circuit to a memory cell may be classified as potentially destructive because a write will change the character of the memory cell. Although an intentional write causes desired data to be stored in the memory cell, an unintentional write or partial write can damage the data contained in the memory cell.
One example in which the above-described problem may occur is in a mask write function for a memory device. The mask write function enables or disables particular write control signals or commands such that the circuit will ignore a write control signal if a mask control signal is in a Mask signal state.
One reason for performing a mask write function is to maintain backward compatibility with data systems as new, more power systems are developed. For example, some newer systems use a wider data format such as a sixteen bit (two byte) word. Thus, there are sixteen bits of storage for each unique address. Older systems may only use 8 bits and would therefore not be able to write the entire double word in one pass. Masking part of the data to protect from an unintended write makes it possible to make full use of the new hardware by using two passes to write two 8 bit words in the addressed double word space.
Another reason for masking is that, in some situations, it is desirable for a processor to change some subset of bits within a word, i.e. to provide the processor with xe2x80x9cbyte addressability.xe2x80x9d One example in which byte addressability is desirable is to implement parity memory. A processor that has byte addressability possesses a write-per-bit function. The mask write function eliminates the need for the processor to change individual bits by performing a Read-Modify-Write cycle, wherein the processor reads all bits from an address location to determine the data stored in the memory location, modifies the bits it wants to change, and then writes the modified information back into the memory location.
When two control signals make transitions between signal states, one control signal may arrive at the logic control circuit later than the other control signal. An unintended consequence of changing signal states in two or more control signals is that the circuit may move from an initial state and enter an intermediate, potentially destructive state upon the arrival of the first control signal, and then move to the intended final state upon the arrival of the second control signal.
Therefore, there is a need in the art to provide a system and method that overcomes these problems.
The above mentioned problems are addressed by the present subject matter and will be understood by reading and studying the following specification. The present subject matter provides for a system and method for preventing late-arriving control signals from initiating an intermediate, potentially destructive state as a logic circuit makes a transition between an initial state and an intended final state. The logic circuit receives two or more input signals or control signals, such as a first input signal and a mask signal. Each of these input signals have two signal states, and each combination of input signal states produces an output signal and corresponds to a logic circuit state. The logic circuit states may be characterized either as non-destructive or potentially destructive, depending on whether a non-destructive or potentially destructive output signal is produced. When two input or control signals make a transition between signal states, both input signal transitions may not be received or detected simultaneously. Therefore, the circuit makes a transition from the initial state, into an intermediate state upon the arrival of the first input signal, and into the final state upon the arrival of the second input signal. The present subject matter directs the circuit through a non-destructive intermediate state. One embodiment presets the latched mask control signal to a Mask signal state after the first control signal makes a transition from an Active signal state to an Idle signal state. Another embodiment periodically resets the first control signal from the Active signal state to the Idle signal state, and presets the mask control signal to the Mask signal state after the first control signal makes a transition from the Active signal state to the Idle signal state.
One aspect provides a circuit, and one embodiment thereof comprises a gate, a first line, a second line and a feedback line. The gate has a first input, a second input and an output. A raw signal is presented to the first input of the gate on the first line. The raw signal makes transitions between two signal states; i.e. an Active signal state and an Idle signal state. A first control signal is presented to the second input of the gate on the second line. The first control signal makes transitions between two signal states; i.e. the Mask signal state and the Unmask signal state. The feedback line latches the output of the gate to the second input of the gate to reset the control signal to the Mask signal state after the raw signal makes a transition from the Active signal state to the Idle signal state.
One embodiment of the circuit comprises a first input node, a second input node, and an output node. A first state signal makes transitions between an Active signal state and an Idle signal state on the first input node. A second state signal makes transitions between a Mask signal state and an Unmask signal state on the second input node. An output signal, corresponding to the first state signal and the second state signal, is generated on the output node. The first state signal and the second state signal provide the circuit with non-destructive states that include an Idle Unmask state, an Idle Mask state, and an Active Mask state. The first state signal and the second state signal further provide at least one potentially destructive state, which corresponds to a potentially destructive output signal, that includes an Active Unmask state. A transition from the non-destructive Idle Unmask state to the non-destructive Active Mask state progresses through the intermediate, non-destructive Idle Mask state rather than through the potentially destructive Active Unmask state.
These and other aspects, embodiments, advantages, and features will become apparent from the following description of the invention and the referenced drawings.